`timescale 1ns/1ns

module breathLed_test;

reg clk;
reg rst_n;
wire led_out;

initial begin
    clk = 1'b0;
    rst_n = 1'b1;
    #100 rst_n = 1'b0;
end

always #10 clk = ~clk;

breathLed dbt
(
    .sys_clk (clk),
    .sys_rst (rst_n),
    .led_out (led_out)
);
    
endmodule